Computer Science Colloquia
Wednesday, August 29, 2012
Advisor: Sudhanva Gurumurthi
Attending Faculty: Kevin Skadron; Mary Lou Soffa; Mircea R. Stan and Joanne Bechta Dugan
10:30 AM, Rice Hall, Rm. 242
Ph.D. Dissertation Presentation
A Multi-Level Approach to NBTI Mitigation in Processors
We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: silicon reliability. Processors have become highly susceptible to a variety of silicon reliability phenomena, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques.
This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the microarchitectural structures in a microprocessor and creates the foundation for understanding NBTI in the context of other physical phenomena that affect the processor. This dissertation consists of tasks that involve modeling, and optimization related to NBTI. The first task involves developing model for NBTI that is usable at the architecture level. Then NBTI mitigation techniques are presented that are developed using that model for the logic and memory structures in the processor and at multiple levels of the design hierarchy. A technique called Recovery Boosting is presented that can significantly enhance NBTI recovery for PMOS devices in memory cells of high-speed SRAM arrays while imposing little performance, area, or power overheads. Then a multi-level optimization approach is presented which combines techniques at the circuit and microarchitecture levels, for reducing the impact of NBTI on the functional units of a high-performance processor core. Finally, an analytical model is presented that captures the interaction between NBTI and process variations.